Summary
Overview
Work History
Education
Skills
Websites
Timeline
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Euijun Cha

Euijun Cha

Senior Integration Engineer

Summary

Senior Integration Engineer with 8 years of experience in DRAM Process and Architecture and Technology Development teams. Specializing in electrical characterization of cell array transistors (Static/dynamic Refresh, tWR, PGE, and Row hammer) and process scheme design for performance enhancement. My current interests are centered on GIDL improvement structures, heat budget-conscious junction formation methods, and maximizing H passivation strategies for next-generation transistors (VCT, 3D DRAM).

Overview

8
8
years of professional experience

Work History

Senior Integration Engineer

Samsung Electronics
09.2017 - Current
  • 1d Node DRAM Development (May 2025 - Present) in the DRAM TD Team.
  • 1c node DRAM Development (Jan. 2021 - Apr. 2025) in the DRAM TD and PA Team: BCAT structure and process design, focusing on Gox scaling and interface state improvement, maximizing dual work-function WL effectiveness, and optimizing N charge/impurity utilization.
  • 1z node DRAM Development (Jan. 2019 - Dec. 2020) in the DRAM PA Team: Tuned Gox process within STI to improve Row Hammer characteristics, and optimized BEOL processes to enhance H passivation.
  • 1y node DRAM Development (Sep. 2017 - Dec. 2018) in the DRAM PA Team: Analysis of electrical device characteristics based on gate oxide formation processes and pre/post-oxide cleaning conditions.

Education

Ph.D. - Material Science And Engineering

Pohang University of Science And Technology (POSTECH)
Pohang-si, Gyeongsangbuk-do, Korea
04.2001 -

Skills

Electrical characterization

DRAM Integration

Gate Oxide Reliability

Timeline

Senior Integration Engineer

Samsung Electronics
09.2017 - Current

Ph.D. - Material Science And Engineering

Pohang University of Science And Technology (POSTECH)
04.2001 -

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Euijun ChaSenior Integration Engineer