Summary
Work History
Education
Skills
Timeline
Generic
Jongho Woo

Jongho Woo

NAND Flash Process Integration Engineer
Hwaseong

Summary

Experienced staff engineer in NAND flash process integration with more than 9+ years designing process flows. Designs and Evaluates process margins with considerations in terms of cost-effectiveness, interactions between modules and productivity.

Work History

Staff Engineer in NAND Flash Process Integration

Samsung
08.2021 - Current
  • Team : future device research lab at R&D center in Hwaseong
  • Designing and evaluating structure of new VNAND cell for N+5 generation.
  • Integrated RRAM(resistive RAM) based VNAND structure which has poly-silicon WL electrodes.
  • Communicated with device analysts and process specialists, optimized next experiments.
  • Integrated FeRAM(ferroelectric RAM) based VNAND structure and characterized its performances.

Staff Engineer in NAND Flash Process Integration

Samsung
06.2019 - 08.2021
  • Team : FLASH TD(Technical Development) at R&D center in Hwaseong
  • V8(8th generation of VNAND) module process integration
  • Integration engineer for lower floored metal-interconnection module and merging two HARC(high aspect ratio contact) etching processes(Through-hole via/Extension channel hole)
  • Reduced entire area of core/peri transistors by sizing down layout design and optimizing integration schemes for that
  • Designed several integration techniques for chip-size reduction scheme in lower floored metal-interconnection module
  • Addressed problems in merging two HARC etching processes by adjusting integration schemes.

Engineer in NAND Flash Process Integration

Samsung
01.2017 - 06.2019
  • Team : FLASH TD(Technical Development) at R&D center in Hwaseong
  • V6(6th generation of VNAND) WL PAD module process integration
  • Designed architecture of cost-effective 5-stairs WL PAD scheme for 6th VNAND
  • Assumed possible process margin issues and addressed challenges from introducing new integration scheme
  • Proposed optimal layout for 5-stairs WL PAD in terms of process margin.

Engineer in NAND Flash Process Integration

Samsung
09.2015 - 12.2016
  • Team name : FLASH PA(Process Architecture) at Pyeongtaek production fab
  • V4(4th generation of VNAND) front-end process integration
  • Optimized process targets in MOLD/ILD/WL PAD modules
  • Simplification of processes in entire front-end module for reducing cost
  • Designed and applied new cost-effective process scheme to 4th generation of VNAND
  • Skipped several simple process steps and merged similar steps together

Engineer in NAND Flash Process Integration

Samsung
08.2014 - 09.2015
  • Team : FLASH TD(Technical Development) at R&D center in Hwaseong
  • V4(4th generation of VNAND) front-end module process integration
  • Process integration in core/peri transistor module
  • Optimized and evaluated current design margins of entire processes
  • Reviewed sizing down transistors for cost effectiveness

Education

M.D. - Semiconductor Device, Energy Harvesting

Korea Advanced Institute of Science And Technology
291 Daehak-ro, Yuseong-gu, Daejeon 34141
04.2001 -

Bachelor of Science - Electrical And Electronics Engineering

Kyungpook National University
80, Daehak-ro, Buk-gu, Daegu, Republic Of Korea
04.2001 -

Skills

Failure Analysis

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Timeline

Staff Engineer in NAND Flash Process Integration

Samsung
08.2021 - Current

Staff Engineer in NAND Flash Process Integration

Samsung
06.2019 - 08.2021

Engineer in NAND Flash Process Integration

Samsung
01.2017 - 06.2019

Engineer in NAND Flash Process Integration

Samsung
09.2015 - 12.2016

Engineer in NAND Flash Process Integration

Samsung
08.2014 - 09.2015

M.D. - Semiconductor Device, Energy Harvesting

Korea Advanced Institute of Science And Technology
04.2001 -

Bachelor of Science - Electrical And Electronics Engineering

Kyungpook National University
04.2001 -

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Jongho WooNAND Flash Process Integration Engineer