JUHEE CHO

- 2018. 3 ~ 2019. 3 Exynos 990 development, GDS-out
* BLK_CPUCL0 / BLK_ALIVE Physical implementation with LN07LPE (back-up)
1) Training / Education for the overall SOC design process
2) Understanding Synthetis / Timing sign-off, Sanity for sign-off
3) Mastering Design-Compiler graphics(DCG), Primetime, VSLP Tool

- 2019. 3 ~ 2020. 8 Google Tensor GS101 development, SF5E GDS-out
* BLK_CPUCL0 / BLK_CMU Physical Implementation with SF5E, PTPX(Low power) analysis, Jitter Improvement
1) A55-DSU-L4 cache interface achieved 1.2GHz, sign-off
2) Jitter improvement within CMU through module separation placement
3) Power strategy implementation with ISO, LS, BLS type cell

- 2020. 9 ~ 2021. 4 Exynos W920 development, GDS-out
* Move to CustomSOC team
* TOP Implementation with SF5E, VSLP analysis
1) TOP Bus implementation, TOP DRC fix
2) BLK_DPUB(MIPI), BLK_MIF(DDRPHY) Implementation reviewer
3) Power strategy implementation of the entire SOC

- 2021. 4 ~ 2021. 2 Google Tensor GS201 development, GDS-out
* BLK_CPUCL0 / SLC(System level cache) / BLK_CMU Physical Implementation with SF5E, Jitter Improvement
1) A55-DSU-L4 cache interface achieved 1.3GHz, sign-off
2) Jitter improvement of the entire SOC(TOP) with ClockFX(Ansys)

- 2021. 2 ~ 2023. 3 Google Tensor GS301 development, GDS-out
* BLK_CPUCL0 / SLC(System level cache) / BLK_CMU Physical Implementation with SF4, Jitter Improvement
1) A55-DSU-L4 cache interface achieved 1.35GHz, sign-off,
2) Design of improved jitter-free clock tree for supplying 3.0 GHz to the BIG CPU
3) Jitter improvement of the entire SOC(TOP) with ClockFX(Ansys)

- 2023. 3 ~ 2023. 6 Exynos V7 development
* Move to SOC PE team
* Conducting BLK reviewer of entire SOC for partners
1) Providing BLK_MIF(DDRPHY), BLK_NOCL0(L4 cache), BLK_DPUB(MIFI) implementation guidance

- 2023. 6 ~ 2023. 11 Google Tensor GS401 development, GDS-out
* BLK_CPUCL0 Physical Implementation with SF4P (BLK_CPUCL0 revision only in GS301)

- 2023. 12 ~ 2024. 02 Dispatching as a senior for SVP

- 2023. 11 ~ 2024. 07 Exynos 2600 development, GDS-out
* NPU Vector Core Physical Implementation with SF2, Power Analysis of entire SOC
1) Building analysis models, methodology for low-power in Oracle DB
2) Improving the NPU pipeline architecture with RTL for timing enhancement

- 2024. 07 ~ Exynos 2700 development
* Setting up the environment for implementation with SF1.4