Jundong KIM

FPGA Design and Implementation of a RISC-V based FP16 Multi-Lane Vector Accelerator for High-Speed, Low-Power SIMD Operations, KyungHee Univ. Graduation Thesis, Korea/ System architecture design / RTL implementation (Verilog) / Clock gating and dynamic lane allocation (Jan. 2025 ~ Jul. 2025)

MXINT Format ALU Synthesis by using Design Compiler, KyungHee Univ. 디지털집적회로모델링실험 class, Korea/ Developed a Python simulator for MXINT data format optimization, designed RTL (MXINT converter / ALU (Nov. 2024 ~ Dec. 2024)

Manually and autonomously controlled RC car with FPGA (Cmod S7), KyungHee Univ. 디지털집적회로모델링실험 class, Korea/ Designed autonomous driving algorithm using IR sensors (including PWM control) in Verilog at RTL / D (Oct. 2024 ~ Nov. 2024)

5X5_SRAM(We_Quatro) Architecture design by using Cadence Tool(45nm freePDK), KyungHee Univ. VLSI Design class, Korea/ Designed 12T SRAM cell with thin-cell layout, Optimized memory cell array for area and delay (Jun. 2025 ~ Jul. 2025)

4X4 Multiplier Architecture by using Cadence Tool (45nm freePDK), KyungHee Univ. VLSI Design class, Korea/ Designed 10T FA, 6T HA for area/delay-optimized layout, and implemented full Vedic Multiplier archit (May. 2025 ~ Jun. 2025)

4×4 MAC processor capable of computing up to 8×8 matrix operations in Verilog at RTL, KyungHee Univ. 디지털회로설계및언어 class, Korea/ Designed a MAC processor based on output-stationary dataflow (Nov. 2024 ~ Dec. 2024)

RISC-TOY: 32-bit Custom RISC Processor Design and RTL Implementation in Verilog, KyungHee Univ. 디지털회로설계및언어 class, Korea/ Designed a 5-stage pipelined RISC_toy processor, Control unit for instruction decoding and pipeline (Sep. 2024 ~ Nov. 2024)

10bit single/differential SAR ADC by using Cadence Tool (SKY130nm PDK), KyungHee Univ. Integrated Circuit class, Korea/ Design of 10-bit SAR ADC (Successive Approximation Register Analog-to-Digital Converter), 2-stage Fo (Apr. 2025 ~ Jun. 2025)

10bit Dual Slope ADC by using Cadence Tool (SKY130nm PDK), KyungHee Univ. Integrated Circuit class, Korea/ 2-stage Folded Cascode Amplifer with CMFB, Bias generator, transistor-level digital logic design etc (Apr. 2025 ~ Jun. 2025)

8bit/10bit capacitive DAC design by using Cadence Tool (SKY130nm PDK), KyungHee Univ. Integrated Circuit class, Korea/ Designed transistor-level digital logic with split capacitor array(counter, switch etc.), 2-stage fo (Apr. 2025 ~ Jun. 2025)