ROHIT PRATAP SINGH

Working with Liberate LV R&D team

• Worked on LV related flows (validate_library and compare_library) for enhancement and bug fixing
• Well versed with all Validation related flows like NLDM ,NLPM , CCSP and glitch validation
• Worked on setup flow for NLDM , NLPM ,CCSP for Samsung with liberate PE team in korea
• Delivered power validation flow fixes for Intel
• Worked closely with PE Korea team for latest Samsung foundary new technology flow setup namely LLE , PSS
• Well versed with all library models namely CCSN , NLDM etc with all new structural changes done to accommodate better accuracy and shorter size of libraries.

Worked on the enhancement and bug fixing for validate_library

• Correction of NLPM flow for Intel libraries
• Achieved 100% correlation for Intel libraries for all cell types
• CCSP bug fixes for wrong charge calculation for mediatek
• Fixed crash issue related to Glich validation for Samsung

Worked on the implementation comparison of new library data types

• LLE and PSS .libs for Samsung
• Variation and sens libs for Intel.

Project 1 - Shannon ( GF40 library )

• Performed extraction of the parasitic netlist for the whole library
• Performed characterisation of the library using synopsys siliconsmart tool to generate various liberty models - NLDM , ECSM ,ECSMN ,CCSN
• Generated EDA views such as - Redhawk , spyglass , voltus , celtic etc
• Written cir and measure files to perform standalone simulations to verify various perimeters of the liberty models such as - Delay , Transition time , Leakage power
• Automated the written cir and measure files to perform multiple simulation at a time for different PVT conditions using shell script
• Calculated tau values for SYNCHRONISER cells to estimate the time required by the cell to come out of metastability state
• Performed standalone simulations for complex cells ( Flip Flops , SYNCHRONISER ) to check the functional correctness at various frequencies

Project 2 - P71 ( GF40 library )

• Performed extraction of netlist with two scenarios ( with and without adding filler and mesh structures ) to study the effect on the delay and transition numbers for the cells
• Performed characterisation of the library for various liberty models - NLDM , CCS , CCSN , ECM ,ECMN
• Performed Multi bit Flip Flop (MBFF) trend analysis to compare 1 bit vs 2/4 bit flops in terms of area , delay and leakage numbers
• Written standalone decs ( cir and measure files) to verify the setup and hold numbers dumped in the liberty models by picking the values from the .lib and inserting it into the waveforms to check for passing/failure case

Project 3 - Realisation of ECO library ( 140nm library )

• Realised new ECO (Engineering change order) library for uhvt flavor
• Migrated the schematics from svt flavor to uhvt by changing the mos models
• Performed extraction of the netlist with qrc tool
• Generated Abstract ( .lef ) view using Abstract generator tool from cadence
• Performed characterization of the library for various liberty models using synopsys siliconsmart tool - NLDM , CCS ,CCSN , ECSM , ECSMN
• Generated EDA views such as - Voltus , Diesel , Verilog views.

Project-1

Objective: Design of Single port High Speed SRAM

• Tools: Spectra, Ezwave and EMC (Zia internal tool)
• Technology: TSMC, 40nm
• Team Size: 3
• Responsibility: Design of single port HSSP SRAM in TSMC 40nm technology
• Architecture Development
• Understanding and working with EMC char flow
• Writing margins and its qualification
• Timing Qualifications
• Timing characterization across PVT and corners
• Lib generation and data sheet generation

Project-2

Objective: HD SRAM Bit Cell and Sense Amp Statistical Analysis

• Tools: hspice
• Technology: TSMC, 40nm
• Responsibility: Sense Analysis: Design and qualification of latch type balanced Sense Amp.which includes Read-0 offset analysis , Read-1 offset analysis , Sense reaction time, Sense pulse width estimation
• Bit cell Analysis: Design and qualification of SRAM bit cell
• It includes SNM qualification , Write margin qualification , Ioff / Ion measurement

Project-3

Objective: Design and Layout of basic standard cells and characterisation

• Tools: Glade ( Layout Editor ) and EMC (Zia internal tool)
• Technology: TSMC, 40nm
• Responsibility: Designed basic standard cells ( AND , NAND , FLOPS ) to meet defined specifications ( delay , transition numbers etc )
• Layout modelling of the designed cells
• DRC and LVS cleaning
• Characterisation using zia internal tool for nldm and ccs models.