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In graduate course, I majored in designing ECC (Error Correction Codes) used in NAND flash. (ECC design especially through NAND flash characteristic)
NAND flash analysis to characterize channel modeling.
Semiconductor Process Integration SK Hynix
Icheon
08.2018 - Current
2018.8~2019.4 : 72-stacks NAND flash memory process integration (256 Gb MLC, 256/512 Gb TLC)
2019.5~2020.1 : 96-stacks NAND flash memory abnormal cell-characteristic analysis (512 Gb TLC)
2020.2~2020.8 : VM (virtual metrology) /w machine learning based on source parameter in equipment machine
2020.9~2020.11 : F16 2D NAND flash memory project management (32 Gb MLC, 4/2/1 Gb SLC)
2020.12~2022.3 : 176-stacks NAND flash memory process integration (1 Tb QLC)
2022.4~present : 238-stacks NAND flash memory process integration (512 Gb/1 Tb TLC)
Show Description Bachelor of Science - Electrical Engineering KAIST
Daejeon, KAIST 02.2007 - 02.2011
Master of Science - Electrical Engineering KAIST
Daejeon, Korea 03.2011 - 02.2013
Ph.D. - Electrical Engineering KAIST
Daejeon, Korea 03.2013 - 07.2018
Show Description
Semiconductor Process Integration SK Hynix
08.2018 - Current
Ph.D. - Electrical Engineering KAIST
03.2013 - 07.2018
Master of Science - Electrical Engineering KAIST
03.2011 - 02.2013
Bachelor of Science - Electrical Engineering KAIST
02.2007 - 02.2011
