Summary
Overview
Work History
Education
Skills
Additional Information
Timeline
Generic
Seung Je Moon

Seung Je Moon

Principal Engineer
Hwaseung

Summary

Accomplished semiconductor engineer with 15+ years of hands-on experience in failure analysis, product diagnostics, and yield enhancement of advanced logic nodes (2–5nm FinFET, 3nm GAA). Currently serving as a Project Manager in the Yield Enhancement (YE) Team within the Foundry Division at Samsung Electronics. Seeking a Foundry Engineer position at Qualcomm to contribute expertise in fault isolation, process optimization, and high-volume manufacturing support.

Overview

14
14
years of professional experience

Work History

Project Manager

Samsung Electronics
08.2023 - Current

- Project Manager in the Yield Enhancement (YE) Team at Samsung Foundry, responsible for yield optimization in advanced logic nodes

- Led mass production yield analysis and prediction for 3nm GAA and 4/5nm FinFET logic products

- Developed and implemented defect & performance BKM with a focus on long-term yield improvement

- Conducted FMEA and YTS trend analysis for process control and risk mitigation

- Identified low-yield root causes, verified improvement effectiveness, and established management standards

- Analyzed process vulnerabilities, managed ramp-up risks, and supported stable high-volume manufacturing

- Delivered internal training sessions on yield forecasting and data analysis

Principal Engineer

GLOBALFOUNDRIES
05.2011 - 06.2023

- QRA & PTF Analysis Group

- Led failure analysis and diagnostic design across technologies and product families

- Conducted static and dynamic fault isolation using OBIRCH, TIVA, EMMI, SDL, JTAG, BIST, and scan chain debug

- Performed physical FA using Meridian IV, SOM4000/5000, FIB, SEM, TEM, CSAM, and X-ray (2D/3D)

- Analyzed GDS layouts (Camelot), test datalogs, and wafer maps to determine root causes of functional and structural failures

- Presented findings and corrective actions to internal teams and global customers

- Designed and validated debug methods for ATE bench systems

Education

Ph.D. - Physics

Kookmin University
Seoul, South Korea
08-2011

Master of Science - Physics

Kookmin University
Seoul, South Korea
02-2007

Bachelor of Science - Physics

Kookmin University
Seoul, South Korea
02-2005

Skills

- Mass Production Yield Analysis & Forecasting (Samsung Foundry, 3nm GAA / 4-5nm FinFET)

- Defect & Performance BKM Discovery and Yield Roadmap Planning

- FMEA, YTS Trend Analysis, and Risk Control for High-Volume Manufacturing

- Process Vulnerability Assessment & Ramp Risk Management - Cross-functional Project Management and Internal Team Training

- Failure Analysis and Root Cause Debug (GlobalFoundries)

- Static & Dynamic Fault Isolation (OBIRCH, TIVA, EMMI, SDL, JTAG, Scan Chain, BIST) - GDS Layout Analysis (Camelot), Wafer Map & Test Datalog Interpretation - Physical Failure Analysis (FIB, SEM, TEM, AFM, X-ray, CSAM) - Diagnostic Design for ATE & Bench Tools (Meridian IV, SOM4000/5000)

Additional Information

Awards & Honors

- Best Poster Award, IPFA 2015

- Long-Service Recognition, GLOBALFOUNDRIES

- Brain Korea Fellowship, 2009–2011


Selected Publications

1. SeungJe Moon, et al. “Enhancing Static Fault Localization with High Pin Count Bench Measurement,” IPFA 2018

2. D. Nagalingam, SeungJe Moon, et al. “Defect Prediction Approach to Enhance Static Fault Localization,” IPFA 2018

3. SeungJe Moon, et al. “Detection of Solder Bump Marginal Contact Resistance,” IPFA 2016

4. SeungJe Moon, et al. “Static Fault Localization on Memory Failures using Photon Emission Microscopy,” IPFA 2015

5. SeungJe Moon, et al. “Soft Defect Localization Technique for SRAM Soft Failure Debug,” ISTFA 2014

Timeline

Project Manager

Samsung Electronics
08.2023 - Current

Principal Engineer

GLOBALFOUNDRIES
05.2011 - 06.2023

Ph.D. - Physics

Kookmin University

Master of Science - Physics

Kookmin University

Bachelor of Science - Physics

Kookmin University
Seung Je MoonPrincipal Engineer