Woosik Kim

Supply Modulator IC Design and Development at S.LSI Business

• Conducted reliability simulations and analyses, including TOTEM, PERC, and PRsim.
• Designed and reviewed evaluation boards, conducted board artwork reviews, and established guidelines for automotive applications and Samsung Galaxy S23, S24, and S24FE product validation.
• Performed automated large-scale chip measurements for internal mass-production approval using Python with lab equipment, including oscilloscopes, DC power supplies, loads, and multimeters.
• Performed EMC (Electromagnetic Compatibility) testing, HTOL (High Temperature Operating Life) tests, and aging tests using environmental chambers and lab equipment.
• Authored technical documents, including datasheets and PCB layout guidelines.
• Managed laboratory operations, including equipment purchases, PC setup, and test software updates.
• Analyzed defects and performed full-layer analysis on legacy products for SMIC.
• Set up and updated Samsung Foundry 90nm PDK (Process Design Kit) for IC design processes.

LDO IP Design and Development for UWB IC at S.LSI Business

• Taped out a complete LDO IP, improving the design with an extended operating temperature range, doubling the maximum load current with only a 16% area increase, achieved by refining the architecture of the over-current protection function, enhancing the slow startup feature, optimizing power transistor sizing, and modifying metal layers and pads to meet rigorous reliability standards.
• Created test vectors to fulfill all IP spec requirements.
• Set up and continuously updated the Samsung Foundry 28nm PDK (Process Design Kit).

HBM Base-Die PHY Design and Development at Memory Business

• Currently designing and developing the PHY circuit for the HBM4 Base-die, with a focus on optimizing write-path margin points, including parity blocks and I/O interfaces.
• Enhanced the architecture to achieve optimal performance, power, and area (PPA) for high-frequency operation at 11.5Gbps.
• Supported automated place-and-route (PnR) flows using Synopsys ICC2.
• Utilized sign-off tools for verification, including PRsim BTI and current strength checks at latch driver points.
• Established verification covering all PVT (Process, Voltage, Temperature) corners, supporting a maximum clock speed of 11.5Gbps.
• Revised the HBM3E B-die to improve margins, enabling reliable qualification.