Yechan Choi

Adept Field Service Engineer with a 6-month tenure at Tokyo Electron Limited Korea, specializing in clean track equipment maintenance and installation. Excelled in enhancing operational efficiencies and troubleshooting complex systems, showcasing proficiency in VHDL, Verilog, and exceptional problem-solving abilities. Demonstrated expertise in analog circuit understanding and a commitment to innovation in semiconductor manufacturing processes.

[Motivation: Low noise, low power design to lead Sony's CIS market]
I applied for Sony Semiconductor Solutions Korea to contribute to the design of Low jitter, Low Power CMOS Image Sensor. With multiple image sensors installed, the importance of reducing the size of image sensors and improving pixels is growing, Sony has established a unique position in image sensor through innovations such as Back Side Illumination and stacking technology. I also want to contribute through Sony's design technology enhancement and CIS design that maximizes signal stability and power efficiency.
The demand for image sensors is increasing not only in smartphone cameras but also in various industries such as ADAS for self-driving cars and X-rays in the medical field. In particular, in CIS design, which requires less noise, high speed, and low power consumption, I want to grow into an engineer who focuses on reducing noise characteristics and power consumption.
At the university, Hspice and Virtuoso tools were used in semiconductor major tracks to conduct Amp, VCO, LDO, DLL design and full-custom layout projects. In particular, the LDO design project implemented a design to reduce the impact of load impedance and reduce power noise by 20% using the Decoupling Capacitor. This experience led me to acquire semiconductor design micro-major.
After graduation, to enhance digital circuit design capabilities, external educational institutions used Verilog to design the Timing Controller of the I2C Protocol and Display.
Based on our experience in designing electronic circuits so far, we will grow into a leading engineer in Sony's CIS market by simultaneously matching high performance and power consumption issues.

[Job suitability: Engineer leading CIS design with Tradeoff analysis and circuit optimization]
Circuit design engineers need tradeoff analysis and improvement ideas and optimization capabilities. These activities have built my circuit design capabilities.
First, we designed the LDO using decoupling cap with Hspice and Virtuoso. To reduce the dropout voltage of the Pass TR, we analyzed the tradeoff that increasing the width resulted in a decrease in speed due to an increase in parasitic cap, and determined the width so that only 0.1V was dropped from the reference voltage. The decoupling cap was used to attenuate the rapid power noise, but the cap value was determined so that the pole's position became a bandwidth of 10 MHz by analyzing the tradeoff that moved at a low frequency. Through this, we have the capability to handle tradeoff in analog circuit design.
Second, the DLL design team project designed the charge pump. We used feedback amp to improve the current mismatch between PMOS and NMOS, which is the cause of jitter. Using 2 stage op amp and adjusting the pole position with Miller compensation for stability, the phase margin ran from 45 degrees to 800 MHz of circuit. After that, when making layout, we improved matching with Multi finger and checked DRC and LVS to match the design and lock time by 93%. Through this, we applied ideas for circuit improvement and optimized layout.
Third, we designed the I2C protocol with Verilog from external training. We conceived the Timing Diagram and FSM, and applied clock-gating and pipelining to improve PPA. This strengthened the ability to optimize PPA with efficient digital design.
Through this experience, we will become a CIS design engineer who reduces the impact of external noise and load and delivers optimal performance.

[Teamwork Case: Setting priorities is the beginning of the design]
By participating in the semiconductor major track, tasks were classified and grouped in the integrated circuit design course, and priorities were determined according to the importance of work. This allowed us to systematically solve problems and achieve goals by organizing the issues that the team needed to discuss.
In a team project of three people for six weeks, we designed Ring VCO to create a clock of 2 GHz by adjusting the cap capacity with the voltage using Varactor. The input voltage range of the blocks in charge of Inverter, Latch, Varactor, etc. was not constant, so the circuit did not operate smoothly. As a result of analyzing and listing various specifications of the circuit such as Power, Bandwidth, and Area, we could not prioritize and missed the key topic. In order to establish the direction of the project, he argued that Bandwidth should be the top priority to organize and analyze the frequency characteristics of each block and match the high frequency clock of 2 GHz. In each face-to-face meeting with the group members twice a week, I completed the task by organizing the priorities of the issues to be discussed in the team.
After the design was completed, the layout was fabricated and the post-SIM was conducted. However, the simulation results showed that the Post-SIM results were inconsistent depending on the device placement, even though the LVS verification was passed. To solve this problem, the common centroid and multi-finger techniques were used to improve the matching between devices. These techniques played an important role in optimizing the physical arrangement of semiconductor devices, maintaining uniform electrical properties and ensuring signal consistency. This resulted in the signal fixation time matching 85% of the original circuit.
Through this project, I became deeply aware of the importance of teamwork in the process of solving problems and achieving goals through cooperation with team members as a leader.

[Aspiration after joining the company: Career Path to go to CIS Expert]
After joining the company, I have the following plan.
First, in the early days of joining the company, I will focus on quickly acquiring the basic skills and processes needed for Sony's CMOS image sensor (CIS) design. I will improve my understanding of Sony's innovative Back Side Illumination technology and stacking technology. I will study the design process of senior employees and analyze the design data, and conduct a seminar presentation on the structure and latest trends of the CIS once a month within the team to improve my understanding of the job. Through small modules or subsystem design projects, I will gain practical experience and learn thorough verification procedures to reduce design errors.
Second, we will play a leading role in the design of the main CIS circuit block and contribute to the low power design and optimization of signal processing performance. In particular, we will realize the design of the CIS with high efficiency by focusing on reducing the noise of the signal and improving the low power characteristics. To this end, we will design the BGR circuit and the low jitter LDO to improve the efficiency and reliability of the Bias voltage and supply voltage used in the CIS and design a solution that can minimize the power noise. We will design a circuit with high PSRR and apply it to the CIS to lower noise and take charge of the circuit design required for AI and autonomous vehicles
In the end, we will eventually establish ourselves as the core CIS technology leader of Sony and grow into an expert leading innovation in high-performance, low-power CIS design. In particular, we will strengthen the competitiveness of CIS in various industries such as autonomous vehicles, medical devices, and smartphones, and develop our capabilities to lead new technological innovations.