Verilog/System verilog
Yeong Gil Jeong
Summary
Dedicated hardware designer with over two years of hands-on experience in memory controller and network on chip design, seeking a CPU Micro-Architect RTL Engineer role at Qualcomm to advance cutting-edge microarchitecture projects and drive innovation in digital system design.
Overview
24
24
years of post-secondary education
Work History
Undergraduate Researcher
IDS Lab, Sungkyunkwan University
12.2023 - Current
- Designed a network on chip (NOC) to facilitate efficient data transfer between HBM and NPU
- Contributed to research publications on efficient data architectures for AI technologies.
- Collaborated with interdisciplinary teams to optimize experimental design and broaden the scope of research projects.
Intern
Samsung Electronics, S.LSI Division
9 2023 - 12.2023
- Modified and designed memory controller IP focusing on scheduler-related enhancements
- Collaborated closely with senior engineers to meet design specifications and timelines.
Education
Bachelor of Science - Electrical Engineering
Sungkyunkwan University
Suwon, South Korea 04.2001 - 05.2025
Skills
Cundefined
Accomplishments
2023 AI Semiconductor Competition — Excellence Award
Activities
Science and Student Council, Sungkyunkwan University, Member, 2022, 2023, Organized and led various educational and social events, enhancing student community engagement.
References
Available upon request.
Projects
DNN Accelerator Design GEMM-based CNN Accelerator
Software
C
Python
Pytorch
Interests
Tutoring
Timeline
Undergraduate Researcher
IDS Lab, Sungkyunkwan University
12.2023 - Current
Bachelor of Science - Electrical Engineering
Sungkyunkwan University
04.2001 - 05.2025
Intern
Samsung Electronics, S.LSI Division
9 2023 - 12.2023
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