Young Hoon Ju

Sony Semiconductor is leading the CMOS image sensor market with its unrivaled technological expertise. Furthermore, I have observed its proactive response to the rapidly growing mobility market with the release of automotive image sensors. This aligns with my values of continuous growth through both theoretical knowledge and design projects. I aspire to provide solutions to customers and society by collaborating with Sony Semiconductor Korea through its top-notch technologies and products.

As an FAE engineer, it is crucial to have a thorough understanding of products and the ability to analyze complex problems from various perspectives. Additionally, strong communication skills with teammates and customers are essential. Through eight team projects, I have honed my ability to clearly convey my ideas, listen to others, and reach agreements. My experiences of analyzing and solving problems based on theoretical knowledge have also taught me perseverance. Leveraging these skills, I aim to serve as a bridge between Sony Semiconductor Korea's image sensor technology and its customers.

I have gained theoretical knowledge about MOSFET operations and digital and analog circuits by taking courses such as electronic circuits, digital logic design, and semiconductor devices. Building upon this foundation, I expanded my practical skills by enrolling in courses like FPGA design and VLSI design to gain hands-on experience in chip design. During this process, I designed a microprocessor and learned how amplifiers, combinational circuits, and sequential circuits are applied to data processing.

Driven by my interest in both hardware and software, I participated in an embedded software school for six months after graduation to further develop my skills. I controlled ultrasonic sensors using the C programming language, enhancing both my programming capabilities and understanding of embedded systems.

By utilizing my experience in electronic circuit design, C programming, and embedded systems, I will gain a deeper understanding of Sony Semiconductor's image sensor characteristics. With this knowledge, I will support customer product porting and effectively address technical inquiries.

I designed an SRAM microprocessor using Cadence Virtuoso, aiming to minimize layout area. During this process, I encountered challenges in designing the XOR gate for the ALU block. I realized that using the structure I had learned in class would not achieve the goal of minimizing the layout area. Consequently, I referenced academic papers and newly designed an XOR gate using two transistors. However, this new design faced an additional issue where the output waveform did not produce strong digital signals.

Through thorough analysis of the circuit diagram and waveform, I identified the root cause: the circuit was not properly connected to VDD and GND. To resolve this, I added a buffer stage to the circuit, successfully designing an XOR gate with an accurate output waveform.

After joining Sony Semiconductor, I will leverage my deep understanding of electronic circuits to comprehend Sony's technologies thoroughly. With this foundation, I will promptly and accurately solve customers' technical issues.

In a team project, I improved project completeness by presenting clear rationales and directions to persuade team members. Using the TOPST D3 board with multi-CPUs, we developed a system to optimize the vehicle's internal environment through situational awareness. My role involved implementing an ultrasonic sensor on the MCU and transmitting the sensing data to the main CPU.

While reviewing the datasheet, I discovered that IPC communication between CPUs was feasible and decided to utilize the relevant API. However, the lack of a guide document made it challenging, as I had to analyze the source code directly to understand the API's usage. One team member suggested using two additional boards to implement a simpler communication method.

To persuade the team, I emphasized the advantages of IPC communication, which would not require modifying the system structure or protocols, and provided a rationale that this approach could save over a week of development time. Recognizing the risk of significant delays in case of failure, I shared analysis results and work plans with the team daily. Additionally, I presented successful test cases demonstrating data transmission and reception, earning the team's agreement.

Ultimately, we successfully established an IPC-based CPU communication interface, reducing development time by a week. Through this process, I developed the ability to derive optimal solutions and consistently communicate with team members based on clear evidence.