Jonghyeon Cho

System Bring up and BSP Initialization

• Experienced in board bring-up and BSP initialization.
• Worked on bootloader development (UBoot) considering hardware revision compatibility and feature scalability.
• Performed PMIC device driver bring-up at the bootloader stage to enable reliable power sequencing and early system initialization.
• Proficient in UART log debugging, bus interface analysis, and early-stage system boot verification to ensure stable hardware-software integration.

Linux Device Driver Development

• Designed and maintained drivers for PMIC (Power Management IC) within the Linux kernel.
• Implemented and maintained device tree configurations to manage hardware abstraction and support multiple board revisions.
• Applied device tree based conditional branching in driver code to ensure compatibility and functional scalability across different hardware platforms.
• Analyzed CPU governors and implemented DVFS (Dynamic Voltage and Frequency Scaling) control mechanisms to balance performance and power efficiency.
• Possess strong understanding of DVFS frameworks for various IPs such as GPU and NPU, enabling system-level power optimization across heterogeneous compute components.
• Enhanced device-level power control stability and performance through continuous driver optimization and kernel-level tuning.

System Power Management

• Developed insights for usage time power management and optimization at the Android OS platform.
• Improved overall system power efficiency through software-level performance tuning and resource control (Linux Scheduler, CPU frequency governor)

Scenario-based Android Power Consumption Management

• Developed adaptive power optimization solutions based on user behavior scenarios.
• Achieved significant energy savings while maintaining device performance.

Systrace Parser Tool Development

• Built and maintained a Python-based server utilizing Android Perfetto to automatically aggregate per-core CPU frequency usage into Excel reports.
• Designed and deployed a GUI tool that reduced manual data analysis time from 1 hour to under 3 minutes, greatly improving workflow efficiency.

Software Associate Architect (Oct 2023)

• Contributed to system architecture design and platform-level decision-making.
• Improved system scalability, modularity, and maintainability across development teams.

Data Science Level 2 Certification (Dec 2023)

• Proficient in big data processing, analysis, and predictive modeling using statistical and machine learning techniques.
• Skilled in data processing and analysis using Python (pandas, NumPy, matplotlib, scikit-learn).
• Capable of developing machine learning–based models for prediction, classification, and optimization tasks.

Best Reviewer (Oct 2024)

• Proposed methodologies for maintaining high-quality code through effective code reviews.
• Practiced Test-Driven Development (TDD) for reliable and maintainable software delivery.

Conducted research on system-level mitigation strategies for cache side-channel attacks using performance counter analysis and machine learning-based detection models.

First author of two peer-reviewed papers on real-time detection of cache side-channel attacks:

• J. Cho et al., “Real-Time Detection for Cache Side Channel Attack using Performance Counter Monitor,” Applied Sciences, vol. 10, no. 1, 2020.
• J. Cho et al., “Real-Time Detection on Cache Side Channel Attacks using Performance Counter Monitor,” ICTC 2019.