KIM MINJAE

- Conducted FIB-SEM and 300mm FIB-SEM process optimization, improving imaging resolution by 20% and reducing analysis time by 30%.
- Developed customized recipes for semiconductor manufacturers (Samsung, SK Hynix), leading to a 25% increase in process stability.
- Provided technical support and troubleshooting, resolving imaging & focus alignment issues and reducing defect rates by 15%.
- Analyzed process data using Excel (pivot tables, SPC, data visualization), detecting error trends and reducing failure rates by 20%.
- Assisted in utilizing AI-based image processing tools for defect detection and process optimization, contributing to a 15% improvement in automated analysis accuracy.
- Collaborated with global teams to enhance equipment performance and automation recipes, decreasing turnaround time (TAT) by 40%.
- Optimized FIB CVD and etching processes, achieving ±5% uniformity in material deposition and improving defect reduction by 30%.

- Developed Cu RDL (Redistribution Layer) process using Nikon Stepper, optimizing exposure dose and focus to achieve ±3% CD uniformity.
- Conducted ASML DUV Stepper-based Hybrid Cu Bonding process development, securing Cu pitch size margin by 35%.
- Optimized wet etching parameters for Cu RDL process, reducing undercut defects by 28% and ensuring target CD dimensions.
- Utilized plasma treatment to enhance CCL warpage reduction and adhesion, improving process stability by 22%.
- Analyzed FIB & V-SEM cross-sections to evaluate etching rate trends and secure reproducibility in Cu RDL fabrication.
- Contributed to Cu CMP process optimization, minimizing dishing and erosion effects and ensuring uniform planarization, reducing dishing by 30%.
- Collaborated with internal teams and external partners to enhance hybrid Cu bonding reliability and advanced packaging process development.

- Developed coordinate system wafers using photolithography, achieving a minimum linewidth of 4μm with 97% pattern clarity.
- Designed custom photomasks for wafer fabrication, optimizing exposure and etching conditions to improve process yield by 60×.
- Conducted 2D material exfoliation on wafers, increasing exfoliation success rate by 40% for semiconductor device fabrication.
- Optimized PR coating and SiO2 etching processes, reducing process defects by 35% and improving resolution consistency.
- Performed FIB and SEM cross-sectional analysis, ensuring etching depth accuracy within ±2% deviation.
- Utilized data visualization techniques to analyze process trends and optimize etching recipes, reducing development time by 30%.
- Assisted in high-temperature wafer processing, resolving process instability issues and enabling a 50% increase in research output, contributing to a successful publication.